The present invention generally relates to MOS devices and the gates employed in such devices. More specifically, the invention relates to asymmetric MOS devices having notched gate oxides.
In digital MOS circuits, performance may be approximated by the ratio of drive current through the circuit to the load being switched by the circuit. EQU f=I/Q
In this expression, I is equal to the drive current through the transistors in the circuit, Q is the charge on the output of a circuit (the load), and f is the operating frequency of the circuit--which is a measure of performance. Thus, a digital circuit's performance can be improved by increasing its drive current and/or decreasing its load.
The drive current is given by the following expression: EQU I=rv
In this expression, r represents the linear charge density (or charge per unit length) in a MOS device channel and v represents the average velocity of the charge carriers in that channel. Thus, current can be increased by increasing either the linear charge density, the charge carrier average velocity, or both along the drive current path in a MOS device.
Charge carriers in conventional MOS devices move in one of two velocity regimes demarcated by the field strength across the device channel. The first regime, known as subsaturation, is encountered at relatively low lateral field strengths, such as are commonly found in long channel devices (e.g., devices in which the effective channel length is greater than about 2 .mu.m). Here velocity increases linearly with the lateral field, e, across the channel. As the lateral field increases, so does the charge carrier velocity. At some point, however, the second velocity regime is reached: a regime referred to as "saturation." Here the increasing lateral field strength has reached or exceeded a critical field strength (ecritical) at which the velocity is no longer a linear function of field strength. Rather the carrier velocity remains constant at a "saturation velocity" (vsat)with increasing field strength. Both vsat and ecritical are material properties of the semiconductor in which conduction takes place.
Typically, velocity saturation is observed in short channel devices (i.e., those devices in which the effective channel length is less than about 1 .mu.m). This is because the source-drain potential drop in such devices takes place over a rather short distance, and therefore the lateral field strength is relatively large.
It should be understood that the carrier velocity described here is actually an average velocity taken over all carriers in the device channel. In most devices, some carriers will be in the saturation regime while others will be in the subsaturation regime.
Physically, at velocity saturation, the carriers have reached a fundamental limit in velocity as determined by their interactions with optical phonons of the semiconductor lattice. Thus, it may appear that, in terms of velocity, no greater performance can be realized beyond saturation velocity. In fact, however, a third velocity regime exists: ballistic transport. This regime exists in systems where the mean free path of the charge carriers is on the order of the distance that the carriers must travel. In single crystal silicon, the mean free path is on the order of about 50 to 1000 .ANG.. At these distances, phonons do not mediate charge carrier transport. Rather, the carriers accelerate under the applied lateral field as if they were in a vacuum so that their velocity increases in proportion to the square root of the potential. Thus at relatively moderate potentials, ballistic electrons can reach velocities greatly exceeding saturation velocity.
Not surprisingly, devices in which ballistic transport plays a significant role may possess greatly improved performance. For silicon-based MOS technology, such devices would have to have an effective channel length of about 0.1 .mu.m (1000 .ANG.) or less. Unfortunately, conventional optical lithography techniques (which are employed to manufacture most MOS integrated circuits today) likely can not produce such small feature sizes without great effort. While X-ray lithography could, in theory, produce devices having such small effective channel lengths, significant technical hurdles remain before feature sizes of this magnitude can be routinely implemented in mass production.
Recently, asymmetric MOS devices fabricated by conventional optical lithographic techniques have been proposed (see the above-referenced U.S. patent application Ser. No. 08/357,436). The channel region in such devices likely can be made short enough that some electrons will move by ballistic transport. These devices include--in addition to conventional MOS device elements--a pocket region of relatively high dopant concentration abutting either the device's source or drain along the side of the source or drain that faces the device's channel region. Because the pocket region abuts only one of the source or drain, the device is deemed "asymmetric."
As explained in U.S. patent application Ser. No. 08/357,436, it is believed that such asymmetric devices behave like two pseudo-MOS devices in series: a "source FET" and a "drain FET," one of which has a higher threshold voltage by virtue of the pocket region. An asymmetric MOS device having such structure will switch on as follows. At a very low (typically less than -1 volt for an NFET) gate voltage, neither the shorter nor longer channel pseudo-device is switched "on." That is, neither pseudo-device's channel region has undergone inversion. However, at slightly higher gate potentials where MOS devices are normally switched off (e.g., about -1 volt), the threshold of the longer channel pseudo-device is exceeded, and that device therefore has switched on. Nevertheless, such gate voltages still do not exceed the level at which the shorter channel pseudo-device switches on. Thus, no current flows between the source and drain yet. As the gate voltage increases and surpasses the shorter channel pseudo-device's threshold voltage (typically at about 0 volts), that device also switches on allowing current to flow between the source and drain. In short, the device switches on in two stages, and does not completely switch on until the gate voltage exceeds the short channel pseudo-device's threshold voltage.
If an asymmetric MOS device is operated such that the gate voltage only slightly exceeds the threshold voltage of the shorter channel pseudo-device, the performance of the overall MOS device will be governed by the performance of that pseudo-device. This is very desirable if the shorter channel pseudo device has an effective channel length on the order of 1000 .ANG. or less. As noted, at such short lengths, some charge carriers ballistically jump across the channel.
While the described asymmetric MOS devices appear to reach the high-performance ballistic transport regime, further performance-improving enhancements to such devices may be attainable.